Dwfpmult

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North Carolina State University **We aren't endorsed by this school
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ECE 464
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Communications
Date
Oct 25, 2023
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8
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Synopsys, Inc. 1 SolvNetPlus DesignWare.com Version DWBB_202203.2 June 2022 Foundation DesignWare Building Blocks > < <= >= - * + > < <= >= - * + DW_fp_mult Floating-Point Multiplier Version, STAR, and myDesignWare Subscriptions: IP Directory Features and Benefits Revision History The precision format is parameterizable for either IEEE single, double precision, or a user-defined custom format Hardware for denormal numbers of IEEE 754 standard is selectively provided. Configurable to be fully compliant with the IEEE Std 754-1985 standard Configurable for NaN representation compatible with the IEEE Std 754-2008 standard (controlled by the ieee_compliance parameter) DesignWare datapath generator is employed for better timing and area Description DW_fp_mult is a floating-point multiplier that multiplies two floating-point values, a and b , to produce a floating-point product, z . Component pins are described in Table 1-1 and configuration parameters are described in Table 1-2 . Table 1-1 Pin Description Pin Name Width Direction Function a exp_width + sig_width + 1 bits Input Multiplier b exp_width + sig_width + 1 bits Input Multiplicand rnd 3 bits Input Rounding mode; supports all rounding modes described in the Datapath Floating-Point Overview z exp_width + sig_width + 1 bits Output Product of a X b status 8 bits Output Status flags corresponding to z ; for details, see STATUS Flags in the Datapath Floating-Point Overview status[6]: Underflow before rounding (UBR) status flag When enabled by the en_ubr_flag parameter, this flag indicates when the absolute value of a non-zero result, computed as though both the exponent range and the precision of the significand were unbounded, would lie strictly between ±MinNorm (minimum normalized value representable in the FP format defined by sig_width and exp_width ). a b rnd z status X
2 Synopsys, Inc. SolvNetPlus DesignWare.com Version DWBB_202203.2 June 2022 DW_fp_mult DesignWare Building Blocks Floating-Point Multiplier For information about the floating-point system defined for all the DW_fp components, including status flag bits, and integer and floating-point formats, refer to the Datapath Floating-Point Overview . Table 1-2 Parameter Description Parameter Values Description sig_width 2 to 253 bits Default: 23 Word length of fraction field of floating-point numbers a , b , and z exp_width 3 to 31 bits Default: 8 Word length of biased exponent of floating-point numbers a , b , and z ieee_compliance 0, 1, or 3 Default: 0 Level of support for the IEEE Std 754 standards: 0: No support for NaNs and denormals; NaNs are considered infinities and denormals are considered zeros 1: Fully compliant with the IEEE Std 754-1985 standard, including support for NaNs and denormals 2: Reserved 3: Fully compliant with the IEEE Std 754-1985 standard plus NaN representation that matches the IEEE Std 754-2008 standard a For details, see Compatibility with IEEE Std 754 Standards in the Datapath Floating-Point Overview a. Propagating payload information to the output during the NaN process, which is an optional feature specified in the IEEE Std 754-2008 standard, is not supported. en_ubr_flag 0 or 1 Default: 0 Controls when the underflow before rounding (UBR) flag in status [6] is enabled 0: The UBR status flag is disabled (the flag is always 0) 1: The UBR status flag is enabled Table 1-3 Synthesis Implementations Implementation Name Function License Feature Required rtl Synthesis model DesignWare str a a. Only available when parameter ieee_compliance is 0. Synthesis model -- delay optimized for non-ieee_compliance DesignWare Table 1-4 Simulation Models Model Function DW02.DW_FP_MULT_CFG_SIM Design unit name for VHDL simulation dw/dw02/src/DW_fp_mult_sim.vhd VHDL simulation model source code dw/sim_ver/DW_fp_mult.v Verilog simulation model source code
Synopsys, Inc. 3 SolvNetPlus DesignWare.com Version DWBB_202203.2 June 2022 DesignWare Building Blocks DW_fp_mult Floating-Point Multiplier Suppressing Warning Messages During Verilog Simulation The Verilog simulation model includes macros that allow you to suppress warning messages during simulation. To suppress all warning messages for all DWBB components, define the DW_SUPPRESS_WARN macro in either of the following ways: Specify the Verilog preprocessing macro in Verilog code: `define DW_SUPPRESS_WARN Or, include a command line option to the simulator, such as: +define+DW_ SUPPRESS_WARN (which is used for the Synopsys VCS simulator) The warning messages for this model include the following: If an invalid rounding mode has been detected on rnd , the following message is displayed: WARNING: < instance_path >: at time = < timestamp >: Illegal rounding mode. To suppress this message, use the DW_SUPPRESS_WARN macro explained earlier. Related Topics Datapath Floating-Point Overview DesignWare Building Block IP User Guide
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